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rev. 4173cs?usb?07/04 features programmable audio output for interfacing with common audio dac ? pcm format compatible ?i 2 s format compatible 8-bit mcu c51 core-based (f max = 20 mhz) 2304 bytes of internal ram 64k bytes of code memory ? at89c5132: flash (100k write/erase cycles) 4k bytes of boot flash memory (at89c5132) ? isp: download from usb or uart to any external memory cards usb rev 1.1 device controller ? ?full speed? data transmission built-in pll multimedia card ? interface compatibility atmel dataflash ? spi interface compatibility ide/atapi interface 2 channels 10-bit adc, 8 khz (8 true bits) ? battery voltage monitoring ? voice recording controlled by software up to 44 bits of general-purpose i/os ? 4-bit interrupt keyboard port for a 4 x n matrix ?smartmedia ? software interface two standard 16-bit timers/counters hardware watchdog timer standard full duplex uart with baud rate generator two wire master and slave modes controller spi master and slave modes controller power management ? power-on reset ? software programmable mcu clock ? idle mode, power-down mode operating conditions ?3v, 10%, 25 ma typical operating at 25c ? temperature range: -40 c to +85 c packages ? tqfp80, plcc84 (development board only) ?dice description the at89c5132 is a mass storage device controlling data exchange between various flash modules, hdd and cd-rom. the at89c5132 includes 64k bytes of flash memory and allows in-system program- ming through an embedded 4k bytes of boot flash memory. the at89c5132 include 2304 bytes of ram memory. the at89c5132 provides all the necessary features for man-machine interface including, timers, keyboard port, serial or parallel interface (usb, spi, ide), adc input, i 2 s output, and all external memory interface (nand or nor flash, smartme- dia, multimedia, dataflash cards). typical applications flash recorder/writer pda, camera, mobile phone pc add-on usb microcontroller with 64k bytes flash memory at89c5132 preliminary summary
4 at89c5132 4173cs?usb?07/04 block diagram figure 1. at89c5132 block diagram notes: 1. alternate function of port 3 2. alternate function of port 4 3. alternate function of port 1 8-bit internal bus clock and pll unit c51 (x2 core) ram 2304 bytes flash interrupt handler unit filt x2 x1 mmc interface i/o mdat p0 - p5 10-bit a-to-d converter v ss v dd keyboard interface kin3:0 i 2 s/pcm audio interface avss av dd ain1:0 ports int0 int1 mosi miso timers 0/1 t1 t0 spi/dataflash controller mclk mcmd sck rst aref dsel dclk sclk dout 64k bytes usb controller d+ d- uart rxd txd ide interface ss watchdog flash boot 4k bytes uvss uv dd and brg 11 11 1 1 2222 3 twi controller scl sda 11
5 at89c5132 4173cs?usb?07/04 pin description figure 2. at89c5132 80-pin tqfp package p0.3/ad3 p0.4/ad4 p0.5/ad5 vss vdd p0.6/ad6 p0.7/ad7 p2.0/a8 p2.1/a9 p3.1/txd p3.2/int0 p3.3/int1 p3.4/t0 p3.0/rxd 1 2 3 4 5 6 7 8 13 11 10 p2.2/a1 0 p2.3/a1 1 p2.4/a1 2 p2.6/a1 4 p2.5/a1 3 p2.7/a1 5 mclk mdat mcmd p0.2/ad2 p0.1/ad1 p0.0/ad0 pvss vss x2 x1 tst vss 9 12 14 15 16 p4.3/ss p4.2/sck p4.1/mosi p4.0/miso vss vdd rst sclk dsel dclk dout ain1 ain0 arefn arefp avss avdd p3.7/rd p3.6/wr p3.5/t1 vdd p1.0/kin0 p1.1/kin1 p1.2/kin2 p1.3/kin3 p1.4 p1.5 p1.7/sda filt pvdd vdd p1.6/scl 17 18 19 20 21 22 23 24 25 26 27 28 33 31 30 29 32 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 53 51 50 49 52 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 73 71 70 69 72 74 75 76 77 78 79 80 ale isp uvdd uvss p5.0 p5.1 p4.7 p4.6 d- d+ p5.3 p5.2 vss vdd p4.5 p4.4 tqfp80
6 at89c5132 4173cs?usb?07/04 figure 3. at89c5132 84-pin plcc (1) note: 1. for development board only. plcc84 p0.3/ad3 p0.4/ad4 p0.5/ad5 vss vdd p0.6/ad6 p0.7/ad7 p2.0/a8 p2.1/a9 p3.3/int1 p3.4/t0 p3.5/t1 p3.6/wr p3.2/int0 65 64 63 62 61 60 59 58 55 56 57 12 13 14 15 16 17 22 20 19 33 34 35 36 37 4 3 2 1 84 83 82 81 80 79 78 nc p2.3/a11 p2.4/a12 p2.6/a14 p2.5/a13 p2.7/a15 mclk mdat mcmd p0.2/ad2 p0.1/ad1 p5.0 pavss vss x2 nc x1 p3.1/txd 18 21 23 24 25 38 39 40 41 42 69 68 67 66 70 5 6 7 8 9 p4.3/ss p4.2/sck p4.1/mosi p4.0/miso vss vdd rst sclk dsel dclk dout ain1 ain0 arefn arefp avss avdd vss vdd p3.7/rd p3.0/rxd p1.0/kin0 p1.1/kin1 p1.2/kin2 p1.3/kin3 p1.4 p1.5 p1.7/sda filt pavdd vdd p1.6/scl 26 43 tst p5.2 p0.0/ad0 77 p2.2/a10 54 ale isp nc p5.1 p4.7 p4.6 76 75 10 11 28 27 29 30 31 32 uvdd uvss 44 45 46 47 48 49 50 51 52 53 74 73 72 71 p4.4 p4.5 vdd vss d- d+ nc p5.3
7 at89c5132 4173cs?usb?07/04 signals all the at89c5132 signals are detailed by functionality in table 1 to table 15. table 1. ports signal description table 2. clock signal description signal name type description alternate function p0.7:0 i/o port 0 p0 is an 8-bit open-drain bidirectional i/o port. port 0 pins that have 1s written to them float and can be used as high impedance inputs. to avoid any parasitic current consumption, floating p0 inputs must be polarized to v dd or v ss . ad7:0 p1.7:0 i/o port 1 p1 is an 8-bit bidirectional i/o port with internal pull-ups. kin3:0 scl sda p2.7:0 i/o port 2 p2 is an 8-bit bidirectional i/o port with internal pull-ups. a15:8 p3.7:0 i/o port 3 p3 is an 8-bit bidirectional i/o port with internal pull-ups. rxd txd int0 int1 t0 t1 wr rd p4.7:0 i/o port 4 p4 is an 8-bit bidirectional i/o port with internal pull-ups. miso mosi sck ss p5.3:0 i/o port 5 p5 is a 4-bit bidirectional i/o port with internal pull-ups. - signal name type description alternate function x1 i input to the on-chip inverting oscillator amplifier to use the internal oscillator, a cr ystal/resonator circuit is connected to this pin. if an external oscillator is used, its output is connected to this pin. x1 is the clock source for internal timing. - x2 o output of the on-chip inverting oscillator amplifier to use the internal oscillator, a cr ystal/resonator circuit is connected to this pin. if an external oscillator is used, leave x2 unconnected. - filt i pll low pass filter input filt receives the rc network of the pll low pass filter. -
8 at89c5132 4173cs?usb?07/04 table 3. timer 0 and timer 1 signal description table 4. audio interface signal description table 5. usb controller signal description table 6. signal name type description alternate function int0 i timer 0 gate input int0 serves as external run control for timer 0, when selected by gate0 bit in tcon register. external interrupt 0 int0 input sets ie0 in the tcon register. if bit it0 in this register is set, bit ie0 is set by a falling edge on int0#. if bit it0 is cleared, bit ie0 is set by a low level on int0#. p3.2 int1 i timer 1 gate input int1 serves as external run control for timer 1, when selected by gate1 bit in tcon register. external interrupt 1 int1 input sets ie1 in the tcon register. if bit it1 in this register is set, bit ie1 is set by a falling edge on int1#. if bit it1 is cleared, bit ie1 is set by a low level on int1#. p3.3 t0 i timer 0 external clock input when timer 0 operates as a counter, a falling edge on the t0 pin increments the count. p3.4 t1 i timer 1 external clock input when timer 1 operates as a counter, a falling edge on the t1 pin increments the count. p3.5 signal name type description alternate function dclk o dac data bit clock - dout o dac audio data - dsel o dac channel select signal dsel is the sample rate clock output. - sclk o dac system clock sclk is the oversampling clock synchronized to the digital audio data (dout) and the channel selection signal (dsel). - signal name type description alternate function d+ i/o usb positive data upstream port this pin requires an external 1.5 k ? pull-up to v dd for full speed operation. - d- i/o usb negative data upstream port -
9 at89c5132 4173cs?usb?07/04 table 7. mutimediacard interface signal description table 8. uart signal description table 9. spi controller signal description table 10. twi controller signal description signal name type description alternate function mclk o mmc clock output data or command clock transfer. - mcmd i/o mmc command line bidirectional command channel used for card initialization and data transfer commands. to avoid any parasitic current consumption, unused mcmd input must be polarized to v dd or v ss . - mdat i/o mmc data line bidirectional data channel. to avoid any parasitic current consumption, unused mdat input must be polarized to v dd or v ss . - signal name type description alternate function rxd i/o receive serial data rxd sends and receives data in serial i/o mode 0 and receives data in serial i/o modes 1, 2 and 3. p3.0 txd o transmit serial data txd outputs the shift clock in serial i/o mode 0 and transmits data in serial i/o modes 1, 2 and 3. p3.1 signal name type description alternate function miso i/o spi master input slave output data line when in master mode, miso receives data from the slave peripheral. when in slave mode, miso outputs data to the master controller. p4.0 mosi i/o spi master output slave input data line when in master mode, mosi outputs data to the slave peripheral. when in slave mode, mosi receives data from the master controller. p4.1 sck i/o spi clock line when in master mode, sck outputs clock to the slave peripheral. when in slave mode, sck receives clock from the master controller. p4.2 ss i spi slave select line when in controlled slave mode, ss enables the slave mode. p4.3 signal name type description alternate function scl i/o twi serial clock when twi controller is in master mode, scl outputs the serial clock to the slave peripherals. when twi controller is in slave mode, scl receives clock from the master controller. p1.6 sda i/o twi serial data sda is the bidirectional two wire data line. p1.7
10 at89c5132 4173cs?usb?07/04 table 11. a/d converter signal description table 12. keypad interface signal description table 13. external access signal description signal name type description alternate function ain1:0 i a/d converter analog inputs - arefp i analog positive voltage reference input - arefn i analog negative voltage reference input this pin is internally connected to avss. - signal name type description alternate function kin3:0 i keypad input lines holding one of these pins high or low for 24 oscillator periods triggers a keypad interrupt. p1.3:0 signal name type description alternate function a15:8 i/o address lines upper address lines for the external bus. multiplexed higher address and data lines for the ide interface. p2.7:0 ad7:0 i/o address/data lines multiplexed lower address and data lines for the external memory or the ide interface. p0.7:0 ale o address latch enable output ale signals the start of an external bus cycle and indicates that valid address information is available on lines a7:0. an external latch is used to demultiplex the address from address/data bus. - isp i/o isp enable input this signal must be held to gnd through a pull-down resistor at the falling reset to force execution of the internal bootloader. - rd o read signal read signal asserted during external data memory read operation. p3.7 wr o write signal write signal asserted during external data memory write operation. p3.6
11 at89c5132 4173cs?usb?07/04 table 14. system signal description table 15. power signal description signal name type description alternate function rst i reset input holding this pin high for 64 oscillator periods while the oscillator is running resets the device. the port pins are driven to their reset conditions when a voltage lower than v il is applied, whether or not the oscillator is running. this pin has an internal pull-down resistor which allows the device to be reset by connecting a capacitor between this pin and v dd . asserting rst when the chip is in idle mode or power-down mode returns the chip to normal operation. - tst i test input test mode entry signal. this pin must be set to v dd . - signal name type description alternate function vdd pwr digital supply voltage connect these pins to +3v supply voltage. - vss gnd circuit ground connect these pins to ground. - avdd pwr analog supply voltage connect this pin to +3v supply voltage. - avss gnd analog ground connect this pin to ground. - pvdd pwr pll supply voltage connect this pin to +3v supply voltage. - pvss gnd pll circuit ground connect this pin to ground. - uvdd pwr usb supply voltage connect this pin to +3v supply voltage. - uvss gnd usb ground connect this pin to ground. -
12 at89c5132 4173cs?usb?07/04 internal pin structure table 16. detailed internal pin structure notes: 1. for information on resistors value, input/output levels, and drive capability, refer to the section ?dc characteristics?, page 183. 2. when the two wire controller is enabled, p 1 , p 2 , and p 3 transistors are disabled allowing pseudo open-drain structure. 3. in port 2, p 1 transistor is continuously driven when outputting a high level bit address (a15:8). circuit (1) type pins input tst input/output rst input/output p1 (2) p2 (3) p3 p4 p53:0 input/output p0 mcmd mdat isp psen output ale sclk dclk dout dsel mclk input/output d+ d- r tst vdd r rst vss p vdd watchdog output p 3 vss n p 1 vdd vdd 2 osc latch output periods p 2 vdd vss n p vdd vss n p vdd d+ d-
13 at89c5132 4173cs?usb?07/04 address spaces the at8xc5132 derivatives implement four different address spaces: program/code memory boot memory data memory special function registers (sfrs) code memory the at89c5132 implements 64k bytes of on-chip program/code memory in flash technology. the flash memory increases rom functionality by enabling in-circuit electrical erasure and programming. thanks to the internal charge pump, the high voltage needed for pro- gramming or erasing flash cells is generated on-chip using the standard v dd voltage. thus, the at89c5132 can be programmed using only one voltage and allows in applica- tion software programming commonly known as iap. hardware programming mode is also available using specific programming tools. boot memory the at89c5132 implements 4k bytes of on-chip boot memory provided in flash tech- nology. this boot memory is delivered programmed with a standard bootloader software allowing in system programming commonly known as isp. it also contains some appli- cation programming interfaces routines commonly known as api allowing user to develop his own bootloader. data memory the at89c5132 derivatives implement 2304 bytes of on-chip data ram. this memory is divided in two separate areas: 256 bytes of on-chip ram memory (standard c51 memory). 2048 bytes of on-chip expanded ram memory (eram accessible via movx instructions).
16 at89c5132 4173cs?usb?07/04 peripherals the at8xc5132 peripherals are briefly described in the following sections. for further details on how to interface (hardware and software) to these peripherals, please refer to the at8xc5132 complete datasheet. clock generator system the at8xc5132 internal clocks are extracted from an on-chip pll fed by an on-chip oscillator. four clocks are generated respectively for the c51 core, the audio interface, and the other peripherals. the c51 and peripheral clocks are derived from the oscillator clock. the audio interface sample rates are also obtained by dividing the pll output clock. ports the at8xc5132 implement five 8-bit ports (p0 to p4) and one 4-bit port (p5). in addition to performing general-purpose i/os, some ports are capable of external data memory operations; others allow for alternate functions. all i/o ports are bidirectional. each port contains a latch, an output driver and an input buffer. port 0 and port 2 output drivers and input buffers facilitate external memory operations. some port 1, port 3 and port 4 pins serve for both general-purpose i/os and alternate functions. timers/counters the at8xc5132 implement the two general-purpose, 16-bit timers/counters of a stan- dard c51. they are identified as timer 0, timer 1, and can independently be configured each to operate in a variety of modes as a timer or as an event counter. when operat- ing as a timer, a timer/counter runs for a programmed length of time, then issues an interrupt request. when operating as a counter, a timer/counter counts negative transi- tions on an external pin. after a preset number of counts, the counter issues an interrupt request. watchdog timer the at8xc5132 implement a hardware watchdog timer that automatically resets the chip if it is allowed to time out. the wdt provides a means of recovering from routines that do not complete successfully due to software or hardware malfunctions. audio output interface the at8xc5132 implements an audio output interface allowing the decoded audio bit- stream to be output in various formats. they are compatible with right and left justification pcm and i 2 s formats and the on-chip pll allows connection of almost all commercial audio dac families available on the market. universal serial bus interface the at8xc5132 implements a full-speed universal serial bus interface. the usb inter- face can be used for the following purposes: download of files by supporting the usb mass storage class. in-system programming by supporting the usb firmware upgrade class. multimedia card interface the at8xc5132 implements a multimedia card (mmc) interface compliant to the v2.2 specification in multimedia card mode. the mmc allows storage of files in removable flash memory cards that can be easily plugged or removed from the application. it can also be used for in-system programming. ide/atapi interface the at8xc5132 provide an ide/atapi interface allowing connection of devices such as cd-rom reader, compactflash ? cards, hard disk drive, etc. it consists of a 16-bit bidi- rectional bus part of the low-level ansi ata/atapi specification. it is provided for mass storage interface but could be used for in-system programming using cd-rom.
17 at89c5132 4173cs?usb?07/04 serial i/o interface the at89c5132 implements a serial port with its own baud rate generator providing one single synchronous communication mode and three full-duplex universal asynchronous receiver transmitter (uart) communication modes. it is provided for the following purposes: in system programming. remote control of the at89c5132 by a host. serial peripheral interface the at89c5132 implements a serial peripheral interface (spi) supporting master and slave modes. it is provided for the following purposes: remote control of the at89c5132 by a host. in system programming. two-wire controller the at89c5132 implements a 2-wire controller supporting the four standard master and slave modes with multimaster capability. it is provided for the following purposes: connection of slave devices like lcd controller, audio dac? remote control of the at89c5132 by a host. in system programming. a/d controller the at89c5132 implements a 2-channel 10-bit (8 true bits) analog to digital converter (adc). it is provided for the following purposes: battery monitoring. voice recording. corded remote control.
18 at89c5132 4173cs?usb?07/04 electrical characteristics absolute maximum ratings dc characteristics digital logic storage temperature ..................................... -65 c to +150 c voltage on any other pin to v ss ..................................... -0.3 to +4.0v i ol per i/o pin ................................................................. 5 ma power dissipation ............................................................. 1 w ambient temperature under bias.................... -40 c to +85 c v dd ....................................................................................... 2.7v to 3.3v note: stressing the device beyond the ?absolute maxi- mum ratings? may cause permanent damage. these are stress ratings only. operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability. table 1. digital dc characteristics v dd = 2.7 to 3.3v , t a = -40 to +85 c symbol parameter min typ (1) max units test conditions v il input low voltage -0.5 0.2v dd -0.1 v v ih1 input high voltage (except rst, x1) 0.2v dd +1.1 v dd v v ih2 input high voltage (rst, x1) 0.7v dd (2) v dd +0.5 v v ol1 output low voltage (except p0, ale, mcmd, mdat, mclk, sclk, dclk, dsel, dout) 0.45 v i ol = 1.6 ma v ol2 output low voltage (p0, ale, mcmd, mdat, mclk, sclk, dclk, dsel, dout) 0.45 v i ol = 3.2 ma v oh1 output high voltage (p1, p2, p3, p4 and p5) v dd -0.7 v i oh = -30 a v oh2 output high voltage (p0, p2 address mode, ale, mcmd, mdat, mclk, sclk, dclk, dsel, dout, d+, d-) v dd -0.7 v i oh = -3.2 ma i il logical 0 input current (p1, p2, p3, p4 and p5) -50 a vin = 0.45 v
19 at89c5132 4173cs?usb?07/04 notes: 1. typical values are obtained using v dd = 3 v and t a = 25 c. they are not tested and there is no guarantee on these values. 2. flash retention is guaranteed with the same formula for v dd min down to 0v. 3. see table 154 for typical consumption in player mode. i dd, i dl and i pd test conditions figure 1. i dd test condition, active mode i li input leakage current (p0, ale, mcmd, mdat, mclk, sclk, dclk, dsel, dout) 10 a 0.45< v in < v dd i tl logical 1 to 0 transition current (p1, p2, p3, p4 and p5) -650 a vin = 2.0 v r rst pull-down resistor 50 90 200 k ? c io pin capacitance 10 pf t a = 25 c v ret v dd data retention limit 1.8 v i dd operating current (3) x1 / x2 mode 6.5 / 10.5 8 / 13.5 9.5 / 17 ma v dd < 3.3 v 12 mhz 16 mhz 20 mhz i dl idle mode current (3) x1 / x2 mode 5.3 / 8.1 6.4 / 10.3 7.5 / 13 ma v dd < 3.3 v 12 mhz 16 mhz 20 mhz i pd power-down mode current 20 500 av ret < v dd < 3.3 v table 1. digital dc characteristics v dd = 2.7 to 3.3v , t a = -40 to +85 c symbol parameter min typ (1) max units test conditions rst tst p0 all other pins are unconnected vdd vdd vdd i dd vdd pvdd uvdd avdd x2 clock signal vss x1 (nc) vss pvss uvss avss
20 at89c5132 4173cs?usb?07/04 figure 2. i dl test condition, idle mode figure 3. i pd test condition, power-down mode x2 vdd clock signal rst vss tst x1 p0 (nc) i dl all other pins are unconnected vss vdd vss vdd pvdd uvdd avdd pvss uvss avss rst mcmd p0 all other pins are unconnected vss vdd tst mdat vdd i pd vdd pvdd uvdd avdd x2 vss x1 (nc) vss pvss uvss avss
21 at89c5132 4173cs?usb?07/04 a-to-d converter table 2. a-to-d converter dc characteristics v dd = 2.7 to 3.3v , t a = -40 c to +85 c oscillator and crystal schematic figure 4. crystal connection note: for operation with most standard crystals, no external components are needed on x1 and x2. it may be necessary to add external capacitors on x1 and x2 to ground in spe- cial cases (max 10 pf). x1 and x2 may not be used to drive other circuits. parameters table 3. oscillator and crystal characteristics v dd = 2.7 to 3.3v , t a = -40 to +85 c symbol parameter min typ max units test conditions av dd analog supply voltage 2.7 3.3 v ai dd analog operating supply current 600 a av dd = 3.3v ain1:0 = 0 to av dd ai pd analog standby current 2 a a v dd = 3.3v aden = 0 or pd = 1 av in analog input voltage av ss a v dd v av ref reference voltage a refn a refp av ss 2.4 a v dd v v r ref aref input resistance 10 30 k ? t a = 25 c c ia analog input capacitance 10 pf t a = 25 c vss x1 x2 q c1 c2 symbol parameter min typ max unit c x1 internal capacitance (x1 - v ss )10pf c x2 internal capacitance (x2 - v ss )10pf c l equivalent load capacitance (x1 - x2) 5 pf dl drive level 50 w f crystal frequency 20 mhz rs crystal series resistance 40 ? cs crystal shunt capacitance 6 pf
22 at89c5132 4173cs?usb?07/04 phase lock loop schematic figure 5. pll filter connection parameters table 4. pll filter characteristics v dd = 2.7 to 3.3v , t a = -40 to +85 c usb connection schematic figure 6. usb connection parameters table 1. usb termination characteristics v dd = 2.7 to 3.3 v, t a = -40 to +85 c in-system programming schematic figure 7. isp pull-down connection parameters table 5. isp pull-down characteristics v dd = 2.7 to 3.3v , t a = -40 to +85 c vss filt r c1 c2 vss symbol parameter min typ max unit r filter resistor 100 ? c1 filter capacitance 1 10 nf c2 filter capacitance 2 2.2 nf d+ d- vbus gnd d+ d- vss to power supply r usb r usb symbol parameter min typ max unit r usb usb termination resistor 27 ? vss isp r isp symbol parameter min typ max unit r isp isp pull-down resistor 2.2 k ?
23 at89c5132 4173cs?usb?07/04 ac characteristics external 8-bit bus cycles definition of symbols table 1. external 8-bit bus cycles timing symbol definitions timings test conditions: capacitive load on all pins = 50 pf. table 2. external 8-bit bus cycle ? data read ac timings v dd = 2.7 to 3.3v, t a = -40 to +85 c signals conditions a address h high d data in l low lale vvalid q data out x no longer valid rrd zfloating wwr symbol parameter variable clock standard mode variable clock x2 mode unit min max min max t clcl clock period 50 50 ns t lhll ale pulse width 2t clcl -15 t clcl -15 ns t avll address valid to ale low t clcl -20 0.5t clcl -20 ns t llax address hold after ale low t clcl -20 0.5t clcl -20 ns t llrl ale low to rd low 3t clcl -30 1.5t clcl -30 ns t rlrh rd pulse width 6t clcl -25 3t clcl -25 ns t rhlh rd high to ale high t clcl -20 t clcl +20 0.5t clcl -20 0.5t clcl +20 ns t av dv address valid to valid data in 9t clcl -65 4.5t clcl -65 ns t avrl address valid to rd low 4t clcl -30 2t clcl -30 ns t rldv rd low to valid data 5t clcl -30 2.5t clcl -30 ns t rlaz rd low to address float 0 0 ns t rhdx data hold after rd high 0 0 ns t rhdz instruction float after rd high 2t clcl -25 t clcl -25 ns
24 at89c5132 4173cs?usb?07/04 table 3. external 8-bit bus cycle ? data write ac timings v dd = 2.7 to 3.3v, t a = -40 to +85 c waveforms figure 1. external 8-bit bus cycle ? data read waveforms symbol parameter variable clock standard mode variable clock x2 mode unit min max min max t clcl clock period 50 50 ns t lhll ale pulse width 2t clcl -15 t clcl -15 ns t avll address valid to ale low t clcl -20 0.5t clcl -20 ns t llax address hold after ale low t clcl -20 0.5t clcl -20 ns t llwl ale low to wr low 3t clcl -30 1.5t clcl -30 ns t wlwh wr pulse width 6t clcl -25 3t clcl -25 ns t whlh wr high to ale high t clcl -20 t clcl +20 0.5t clcl -20 0.5t clcl +20 ns t avwl address valid to wr low 4t clcl -30 2t clcl -30 ns t qvwh data valid to wr high 7t clcl -20 3.5t clcl -20 ns t whqx data hold after wr high t clcl -15 0.5t clcl -15 ns t avdv t llax t rhdx t rhdz t av ll t avrl p2 p0 rd ale t lhll t rlrh data in a15:8 t rlaz t llrl t rhlh t rldv d7:0 a7:0
25 at89c5132 4173cs?usb?07/04 figure 2. external 8-bit bus cycle ? data write waveforms external ide 16-bit bus cycles definition of symbols table 4. external ide 16-bit bus cycles timing symbol definitions timings test conditions: capacitive load on all pins = 50 pf. t whlh t avwl t llax t whqx p2 p0 wr ale t lhll t wlwh a15:8 t av ll t qvwh d7:0 data out t llwl a7:0 signals conditions a address h high d data in l low lale vvalid q data out x no longer valid rrd zfloating wwr
26 at89c5132 4173cs?usb?07/04 table 5. external ide 16-bit bus cycle ? data read ac timings v dd = 2.7 to 3.3v, t a = -40 to +85 c table 6. external ide 16-bit bus cycle ? data write ac timings v dd = 2.7 to 3.3v, t a = -40 to +85 c symbol parameter variable clock standard mode variable clock x2 mode unit min max min max t clcl clock period 50 50 ns t lhll ale pulse width 2t clcl -15 t clcl -15 ns t avll address valid to ale low t clcl -20 0.5t clcl -20 ns t llax address hold after ale low t clcl -20 0.5t clcl -20 ns t llrl ale low to rd low 3t clcl -30 1.5t clcl -30 ns t rlrh rd pulse width 6t clcl -25 3t clcl -25 ns t rhlh rd high to ale high t clcl -20 t clcl +20 0.5t clcl -20 0.5t clcl +20 ns t avdv address valid to valid data in 9t clcl -65 4.5t clcl -65 ns t avrl address valid to rd low 4t clcl -30 2t clcl -30 ns t rldv rd low to valid data 5t clcl -30 2.5t clcl -30 ns t rlaz rd low to address float 0 0 ns t rhdx data hold after rd high 0 0 ns t rhdz instruction float after rd high 2t clcl -25 t clcl -25 ns symbol parameter variable clock standard mode variable clock x2 mode unit min max min max t clcl clock period 50 50 ns t lhll ale pulse width 2t clcl -15 t clcl -15 ns t avll address valid to ale low t clcl -20 0.5t clcl -20 ns t llax address hold after ale low t clcl -20 0.5t clcl -20 ns t llwl ale low to wr low 3t clcl -30 1.5t clcl -30 ns t wlwh wr pulse width 6t clcl -25 3t clcl -25 ns t whlh wr high to ale high t clcl -20 t clcl +20 0.5t clcl -20 0.5t clcl +20 ns t avwl address valid to wr low 4t clcl -30 2t clcl -30 ns t qvwh data valid to wr high 7t clcl -20 3.5t clcl -20 ns t whqx data hold after wr high t clcl -15 0.5t clcl -15 ns
27 at89c5132 4173cs?usb?07/04 waveforms figure 3. external ide 16-bit bus cycle ? data read waveforms note: d15:8 is written in dat16h sfr. figure 4. external ide 16-bit bus cycle ? data write waveforms note: d15:8 is the content of dat16h sfr. spi interface definition of symbols table 7. spi interface timing symbol definitions t avdv t llax t rhdx t rhdz t avll t avrl p2 p0 rd ale t lhll t rlrh data in t rlaz t llrl t rhlh t rldv d7:0 a7:0 data in d15:81 a15:8 t whlh t avwl t llax t whqx p2 p0 wr ale t lhll t wlwh t avll t qvwh d7:0 data out t llwl a7:0 d15:81 data out a15:8 signals conditions c clock h high i data in l low o data out v valid x no longer valid zfloating
28 at89c5132 4173cs?usb?07/04 timings table 8. spi interface master ac timing v dd = 2.7 to 3.3v, t a = -40 to +85 c notes: 1. value of this parameter depends on software. 2. test conditions: capacitive load on all pins = 100 pf symbol parameter min max unit slave mode t chch clock period 8 t osc t chcx clock high time 3.2 t osc t clcx clock low time 3.2 t osc t slch , t slcl ss low to clock edge 200 ns t ivcl , t ivch input data valid to clock edge 100 ns t clix , t chix input data hold after clock edge 100 ns t clov, t chov output data valid after clock edge 100 ns t clox , t chox output data hold time after clock edge 0 ns t clsh , t chsh ss high after clock edge 0 ns t ivcl , t ivch input data valid to clock edge 100 ns t clix , t chix input data hold after clock edge 100 ns t slov ss low to output data valid 130 ns t shox output data hold after ss high 130 ns t shsl ss high to ss low (1) t ilih input rise time 2 s t ihil input fall time 2 s t oloh output rise time 100 ns t ohol output fall time 100 ns master mode t chch clock period 4 t osc t chcx clock high time 1.6 t osc t clcx clock low time 1.6 t osc t ivcl , t ivch input data valid to clock edge 50 ns t clix , t chix input data hold after clock edge 50 ns t clov, t chov output data valid after clock edge 65 ns t clox , t chox output data hold time after clock edge 0 ns t ilih input data rise time 2 s t ihil input data fall time 2 s t oloh output data rise time 50 ns t ohol output data fall time 50 ns
29 at89c5132 4173cs?usb?07/04 waveforms figure 5. spi slave waveforms (sscpha = 0) note: 1. not defined but generally the msb of the character which has just been received. figure 6. spi slave waveforms (sscpha = 1) note: 1. not defined but generally the lsb of the character which has just been received. t slcl t slch t chcl t clch mosi (input) sck (sscpol = 0) (input) ss (input) sck (sscpol = 1) (input) miso (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t chov t clov t chox t clox msb in bit 6 lsb in slave msb out slave lsb out bit 6 t slov 1 t shox t shsl t chsh t clsh si (input) sck (sscpol = 0) (output) ss 1 (output) sck (sscpol = 1) (output) so (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t chov t clov t chox t clox msb in bit 6 lsb in msb out port data lsb out port data bit 6 t chcl t clch
30 at89c5132 4173cs?usb?07/04 figure 7. spi master waveforms (sscpha = 0) note: 1. ss handled by software using general purpose port pin. figure 8. spi master waveforms (sscpha = 1) note: 1. ss handled by software using general purpose port pin. t chcl t clch mosi (input) sck (sscpol = 0) (input) ss 1 (input) sck (sscpol = 1) (input) miso (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t clov t chov t clox t chox msb in bit 6 lsb in slave msb out slave lsb out bit 6 t slov 1 t shox t shsl t chsh t clsh t slcl t slch si (input) sck (sscpol = 0) (output) ss 1 (output) sck (sscpol = 1) (output) so (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t chov t clov t chox t clox msb in bit 6 lsb in msb out port data lsb out port data bit 6 t chcl t clch
31 at89c5132 4173cs?usb?07/04 two-wire interface timings table 1. twi interface ac timing v dd = 2.7 to 3.3 v, t a = -40 to +85 c notes: 1. at 100 kbit/s. at other bit-rates this value is inversely proportional to the bit-rate of 100 kbit/s. 2. determined by the external bus-line capacitance and the external bus-line pull-up resistor, this must be < 1 s. 3. spikes on the sda and scl lines with a duration of less than 3t clcl will be filtered out. maximum capacitance on bus-lines sda and scl= 400 pf. 4. t clcl = t osc = one oscillator clock period. waveforms figure 9. two wire waveforms symbol parameter input m i n max output m i n max t hd ; sta start condition hold time 14t clcl (4) 4.0 s (1) t low scl low time 16t clcl (4) 4.7 s (1) t high scl high time 14t clcl (4) 4.0 s (1) t rc scl rise time 1 s- (2) t fc scl fall time 0.3 s0.3 s (3) t su ; dat1 data set-up time 250 ns 20t clcl (4) - t rd t su ; dat2 sda set-up time (before repeated start condition) 250 ns 1 s (1) t su ; dat3 sda set-up time (before stop condition) 250 ns 8t clcl (4) t hd ; dat data hold time 0 ns 8t clcl (4) - t fc t su ; sta repeated start set-up time 14t clcl (4) 4.7 s (1) t su ; sto stop condition set-up time 14t clcl (4) 4.0 s (1) t buf bus free time 14t clcl (4) 4.7 s (1) t rd sda rise time 1 s - (2) t fd sda fall time 0.3 s0.3 s (3) tsu ;d at 1 t su ;sta ts u ; d at 2 t hd ;sta t high t low sda (input/output) 0.3 v dd 0.7 v dd t buf t su ;sto 0.7 v dd 0.3 v dd t rd t fd t rc t fc scl (input/output) t hd; dat t su; dat3 start or repeated start condition start condition stop condition repeated start condition
32 at89c5132 4173cs?usb?07/04 mmc interface definition of symbols table 9. mmc interface timing symbol definitions timings table 10. mmc interface ac timings v dd = 2.7 to 3.3 v, t a = -40 to +85 c, cl 100pf (10 cards) waveforms figure 10. mmc input output waveforms signals conditions c clock h high d data in l low o data out v valid x no longer valid symbol parameter min max unit t chch clock period 50 ns t chcx clock high time 10 ns t clcx clock low time 10 ns t clch clock rise time 10 ns t chcl clock fall time 10 ns t dvch input data valid to clock high 3 ns t chdx input data hold after clock high 3 ns t chox output data hold after clock high 5 ns t ovch output data valid to clock high 5 ns t ivch mclk mdat input t chch t clcx t chcx t chcl t clch mcmd input t chix t ovch mdat output mcmd output t chox
33 at89c5132 4173cs?usb?07/04 audio interface definition of symbols table 11. audio interface timing symbol definitions timings table 12. audio interface ac timings v dd = 2.7 to 3.3v, t a = -40 to +85 c, cl 30pf note: 32-bit format with fs = 48 khz. waveforms figure 11. audio interface waveforms signals conditions c clock h high o data out l low s data select v valid x no longer valid symbol parameter min max unit t chch clock period 325.5 (1) ns t chcx clock high time 30 ns t clcx clock low time 30 ns t clch clock rise time 10 ns t chcl clock fall time 10 ns t clsv clock low to select valid 10 ns t clov clock low to data valid 10 ns dclk t chch t clcx t chcx t clch t chcl dsel ddat right left t clsv t clov
34 at89c5132 4173cs?usb?07/04 analog to digital converter definition of symbols table 13. analog to digital converter timing symbol definitions characteristics table 2. analog to digital converter ac characteristics v dd = 2.7 to 3.3 v, t a = -40 to +85 c notes: 1. av dd = av refp = 3.0 v, av ss = av refn = 0 v. adc is monotonic with no missing code. 2. the differential non-linearity is the difference between the actual step width and the ideal step width (see figure 23). 3. the integral non-linearity is the peak difference between the center of the actual step and the ideal transfer curve after appropriate adjustment of gain and offset errors (see figure 23). 4. the offset error is the absolute difference between the straight line which fits the actual transfer curve (after removing of gain error), and the straight line which fits the ideal transfer curve (see figure 23). 5. the gain error is the relative difference in percent between the straight line which fits the actual transfer curve (after removing of offset error), and the straight line which fits the ideal transfer curve (see figure 23). waveforms figure 12. analog-to-digital converter internal waveforms signals conditions c clock h high e enable (aden bit) l low s start conversion (adsst bit) symbol parameter min max unit t clcl clock period 4 s t ehsh start-up time 4 s t shsl conversion time 11t clcl s dle differential non- linearity error (1)(2) 1lsb ile integral non- linearity errorss (1)(3) 2lsb ose offset error (1)(4) 4lsb ge gain error (1)(5) 4lsb aden bit adsst bit t ehsh t shsl clk t clcl
35 at89c5132 4173cs?usb?07/04 figure 13. analog-to-digital converter characteristics flash memory definition of symbols table 14. flash memory timing symbol definitions timings table 15. flash memory ac timing v dd = 2.7 to 3.3v, t a = -40 to +85 c 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 offset error code out avin (lsbideal) ose offset error ose gain error ge ideal transfer curve 1 lsb (ideal) integral non-linearity (ile) differential non-linearity (dle) center of a step example of an actual transfer curve 0 0 signals conditions sisp l low rrst vvalid b fbusy flag x no longer valid symbol parameter min typ max unit t svrl input isp valid to rst edge 50 ns t rlsx input isp hold after rst edge 50 ns t bhbl flash internal busy (programming) time 10 ms n fcy number of flash write cycles 100k cycle t fdr flash data retention time 10 year
36 at89c5132 4173cs?usb?07/04 waveforms figure 14. flash memory ? isp waveforms note: 1. isp must be driven through a pull-down resistor (see section ?in-system program- ming?, page 22). figure 15. flash memory ? internal busy waveforms external clock drive and logic level references definition of symbols table 16. external clock timing symbol definitions timings table 17. external clock ac timings v dd = 2.7 to 3.3v, t a = -40 to +85 c waveforms figure 16. external clock waveform rst t svrl isp (1) t rlsx fbusy bit t bhbl signals conditions c clock h high l low x no longer valid symbol parameter min max unit t clcl clock period 50 ns t chcx high time 10 ns t clcx low time 10 ns t clch rise time 3 ns t chcl fall time 3 ns t cr cyclic ratio in x2 mode 40 60 % 0.45 v t clcl v dd - 0.5 v ih1 v il t chcx t clch t chcl t clcx
37 at89c5132 4173cs?usb?07/04 figure 17. ac testing input/output waveforms notes: 1. during ac testing, all inputs are driven at v dd -0.5v for a logic 1 and 0.45v for a logic 0. 2. timing measurements are made on all outputs at v ih min for a logic 1 and v il max for a logic 0. figure 18. float waveforms note: for timing purposes, a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float wh en a 100 mv change from the loading v oh /v ol level occurs with i ol /i oh = 20 ma. 0.45 v v dd - 0.5 0.7 v dd 0.3 v dd v ih min v il max inputs outputs v load v oh - 0.1v v ol + 0.1v v load + 0.1v v load - 0.1v timing reference points
38 at89c5132 4173cs?usb?07/04 ordering information note: 1. plcc84 package only available for development board. possible order entries (1) part number memory size (bytes) supply voltage temperature range max frequency (mhz) package packing product marking at89c5132-rotil 64k flash 3v industrial 40 tqfp80 tray 895132-il
39 at89c5132 4173cs?usb?07/04 package information tqfp80
40 at89c5132 4173cs?usb?07/04 plcc84
41 at89c5132 4173cs?usb?07/04 datasheet change log for at89c5132 changes from 4173a- 08/02 to 4173b-03/04 1. supression of rom product version. 2. supression of tqfp64 package. changes from 4173b- 03/04 - 4173c - 07/04 1. add usb connection schematic in usb section. 2. add usb termination characteristics in dc characteristics section. 3. page access mode clarification in data memory section.
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